A clock source in a first area of a chip may be used to provide an extended clock in a different area of the chip or even off-chip to implement a synchronous data transfer. For example, in a memory controller, system memory clocks for off-chip memory are typically generated off of a host clock from the memory controller.
With reference to FIG. 1, a circuit for generating an extended clock is generally shown. It comprises a phase locked loop (PLL) 102 that receives a clock reference signal (REF CLK) and from it generates an output clock signal that drives a clock tree 104. The PLL 102 also receives a feedback signal tapped from the clock output downstream from the clock tree 104, through an extended feedback path 107, to track the output clock signal against the reference clock. (Feedback path 107 is referred to as being “extended” because it is relatively long due to the robust nature of the clock tree 104.) The output clock signal is driven through clock driver 106 and provided as an extended clock signal (EXT CLK). Unfortunately, with the feedback path 107 being relatively long and proximal to the clock tree 107, the CLK signal may be noisy an susceptible to jitter, which is transferred to the extended clock signal. This can be especially problematic for extended clock signals used for system memory clocks.
FIG. 2 shows a block diagram of a clock generator in a memory controller core 201 used to drive local clock trees and to provide the system memory clock through I/O interface 211 to off-chip memory devices. It has a PLL 202 in the Memory Controller Core 201. The PLL 202 receives a reference clock (REF CLK) and from that generates a host clock signal (Host CLK) at first and second outputs to clock trees in first and second domains 204A, 204B. The output clock loads (including the clock trees) are matched to one another. An extended feedback path 207 is provided from the output of the first domain clock tree 204A back to the PLL 202 to track the Host CLK signal against the REF CLK signal. The Host CLK signals also drive flip flops 207A, 207B and decision logic 209 to transmit data (not shown) to the IO Interface 211 through data flip-flop 213 and data driver 216. The Host CLK signal is also driven through clock driver 218 to provide an extended version of the Host CLK signal (EXT Host CLK).
Thus, the MC Core PLL 202 generates the system memory clock, as well as the host clock, which is used as the source for the system memory clock. This simplifies timing relationships between the memory controller and system memory interface, but with the feedback being tapped downstream from the clock trees (which may be relatively large), any low frequency noise in the memory controller core can influence the behavior of the PLL and in turn, the quality of the system memory clock. Even more problematic, however, high frequency noise also impacts the system memory clock making it difficult to meet performance requirements such as jitter.
Accordingly, an improved extended clock solution may be desired.